Increasing power densities in the development of modules and converters lead to ever higher semiconductor temperatures. To ensure reliability of components,
thermal optimization between the semiconductor chip and the heat sink is becoming increasingly important (chip optimization, layout optimization). Through
a simulation problems can be detected in advance and avoided, as well as development costs can be saved. The thermal-electrical simulation software developed
by Zth-Messtechnik Kiffe for 2-level inverters based on "measurements" allows the user to simulate the junction temperature of the individual semiconductor
chips in a power module very accurately in the time domain.
New: The software is now also available as Dynamic Link Library (DLL). By integrating this library into numerical simulation programs, it is possible to simulatecomplex converter-fed drives.
The following measurement results are integrated in the 2-level inverter simulation software:
- Forward voltage measurements of all IGBTs and diodes in the phase module at different temperatures (including the voltage drops in the module)
- Switching measurements of IGBT and diode in the phase module at different load currents and temperatures (Uschalt = Uzk)
- Zth-measurements of all IGBTs and diodes in the phase module, as well as transient thermal coupling measurements between all IGBTs and diodes
(4 Zth-measurements + 12 coupling measurements)
Example: transient thermal coupling in the phase module (IGBT T1)
The picture shows the cooling curves of the different IGBTs and diodes in the phase module after switching off the load current of T1. The cooling curves
were created from the extracted R/C elements of the measurement curve. The chip layout image shows the spatial position of the various IGBTs and diodes.
Cooling: closed water cooler, heating/cooling time: 100s each.
2-level-inverter-simulation model with 3-phase asynchronous motor:
T1, T2, D1, D2=module phase U
T3, T4, D3, D4=module phase V
T5, T6, D5, D6=module phase W
Structure simulation program:
Rs1, Rs2, Rs3=stator resistance
Ls1, Ls2, Ls3=stator inductance
Lh1, Lh2, Lh3=main inductance
Lr1, Lr2, Lr3=rotor inductance
Rr1, Rr2, Rr3=rotor resistance
Rschl1, Rschl2, Rschl3=slip resistance
Set increment=10ns, Error of approx. 0,3% in the current calculation against a step size of 2ns
Inductance Ls1=Ls2=Ls3, Lh1=Lh2=Lh3, Lr1=Lr2=Lr3Resistance Rs1=Rs2=Rs3, Rr1=Rr2=Rr3no dead times during undershoot proceduresBlock losses at T1, T2, D1, D2 always 0W(measurement: T1/D1 (each 3 chips) at 700V/125°C = 0,19W)no temperature calculation for transistors and diodes in phase V and phase W
temperature for the transistors in phase V and phase W is calculated from mean of T1 and T2
temperature for the freewheeling diodes in phase V and phase W is calculated from mean of D1 and D2Simulation results:
2-level-IGBT-phasen module 450A/1200VUo=700VHeatsink: closed water cooler with waffle structure insert
Thermal Compounds: silicone-free
Cooling medium: water 8l/minSimulation time=0-100s, increment=10ns
Modulation rate=0,75Modulations: undershoot method
Starting temperature (Tamb)=25,00°C
Stator inductance Ls1/Ls2/Ls3=0,195mH
Main inductance Lh1/Lh2/Lh3=11,1mH
Rotor inductance Lr1/Lr2/Lr3=0,238mH
Stator resistance Rs1/Rs2/Rs3=15,8mΩ
Rotor resistance Rr1/Rr2/Rr3=10mΩ
The graph shows the simulated junction temperatures of the 4 semiconductors in the time range between 99,995s and 100s (2 periods). Looking at thesimulation comparison of closed water cooler / open water cooler, you can see that by the right choice of the heat sink a much more efficient coolingof the semiconductor is possible (same flow, same pressure drop).